This invention relates generally to electronic devices, and more specifically to a method for conditioning a substoichiometric metal oxide dielectric layer of a capacitor useful in semiconductor devices such as dynamic random access memories (DRAMs).
As semiconductor manufacturing technology has progressed and the applications of memory devices have expanded, numerous highly integrated memory devices have been developed. One such memory device is dynamic random access memory (DRAM). In general, DRAM consists of an array of memory cells which are accessed by peripheral circuitry that randomly reads and writes information to and from individual memory cells. The most common type of DRAM cell consists of a single transistor and a single capacitor connected in series. The capacitor stores a bit of data as an electrical charge, and the transistor allows for selective charging and discharging of the capacitor.
A capacitor, in its simplest form, consists of two conducting electrode surfaces separated by an insulating dielectric material. In the early development of the semiconductor capacitor, a doped substrate was used as the first electrode, silicon dioxide was used as the dielectric material, and a metal layer was used as the second electrode. More recently, and due to technological advances, the capacitor electrodes are now commonly made from materials such as polysilicon, epitaxial silicon, silicides, salicides, as well as several metals including osmium, rhodium, platinum, gold, ruthenium, and aluminum, while the capacitor dielectric is now commonly made from materials such as oxide-nitride-oxide (ONO), tantalum pentoxide, and lead zirconium titanate.
Among these new dielectric materials, tantalum pentoxide is perhaps the most widely studied and commercially developed. Tantalum pentoxide is an advantageous capacitor dielectric material because it has a dielectric constant which is approximately six to eight times greater than that of silicon dioxide. Thus, as the size of memory cells shrink, the capacitance can be maintained at a high level needed for device performance. Because of the demand for denser and more highly integrated memory devices, smaller DRAM cells are very desirable.
A problem exists, however, with the electrical characteristics of metal oxide dielectric layers applied by most conventional semiconductor processing techniques. Typically, metal oxide is applied to a first capacitor electrode of a semiconductor device by either chemical vapor deposition (CVD) or by sputtering. Both of these techniques, however, result in a metal oxide layer which tends to be oxygen deficient. That is, the ratio of oxygen to metal atoms tends to be lower than the metal oxide""s stoichiometric ratio; hence, the metal oxide dielectric layer prepared by either of these two conventional techniques will be substoichiometric. A substoichiometric metal oxide dielectric layer has a higher leakage current and a lower breakdown voltage than a fully oxidized or stoichiometric metal oxide dielectric layer. Until recently, these undesirable electrical characteristics associated with substoichiometric metal oxide layers have limited their use as capacitor dielectrics in DRAM cells.
The literature discloses several methods which seek to improve the undesirable electrical characteristics of one type of metal oxide dielectric layer, namely, tantalum pentoxide. For example, rapid thermal oxidation (RTO), ultraviolet (UV) ozone, and low temperature ozone plasma annealing of a tantalum pentoxide dielectric layer have all been reported. These methods all attempt to more fully oxidize a substoichiometric tantalum pentoxide layer into a fully or substantially stoichiometric composition. A discussion of these methods is provided in U.S. Pat. No. 5,468,687 issued to Carl et al., and in U.S. Pat. No. 5,142,438 issued to Reinberg et al. There are, however, several disadvantages associated with each of these methods. For example, the rapid thermal oxidation method utilizes high temperatures which can damage the underlying semiconductor substrate, including the substrate""s various components. Specifically, the high temperatures used in this method have been found to damage the underlying polysilicon conductive layer, thereby degrading the capacitor""s dielectric properties. Similarly, the ultraviolet ozone method has been found to induce local regions of high temperature which can also damage the polysilicon conductive layer. Finally, although the low temperature ozone plasma annealing method is performed at low temperatures (i.e., approximately 400xc2x0 C.) and is therefore not damaging to the underlying polysilicon conductive layer, it nevertheless requires relatively sophisticated and expensive processing equipment.
Another method that the literature discloses to improve the electrical properties of a tantalum pentoxide layer is to dope it with titanium dioxide. A discussion of tantalum pentoxide doping and its limitations is provided in U.S. Pat. No. 5,189,503 issued to Suguro et al, and in an article entitled xe2x80x9cElectrical Properties of Thin Ta2O5 Films Grown by Chemical Vapor Depositionxe2x80x9d, at pp. 680-683 of the IEDM Technical Digest (1986), by Saito et al. The primary limitation with doping tantalum pentoxide with titanium dioxide is that it only partially solves the oxygen deficiency problem due to solubility limitations of titanium. As a result, tantalum pentoxide doped with titanium dioxide still has a higher than desired leakage current.
Accordingly, there exists a need for a method to fully oxidize a substoichiometric metal oxide dielectric layer, such as tantalum pentoxide, into a stoichiometric composition in a practical and effective manner. The present invention fulfills this need by providing a new low temperature method for conditioning a metal oxide layer to form a more highly oxidized layer, and provides further related advantages as disclosed in more detail herein.
In a first aspect, the invention provides a method of forming a memory cell. The method includes the step of providing a substrate having a transistor on a first portion of the substrate and a first conductive layer on a second portion of the substrate. The transistor has a first electrode. The method further includes the step of forming a dielectric layer containing substoichiometric tantalum pentoxide having a first oxygen content, the dielectric layer overlying the first conductive layer; conditioning the dielectric layer with sulfur trioxide to define a more highly oxidized tantalum pentoxide layer having a second oxygen content, where the second oxygen content is greater than the first oxygen content; forming a second conductive layer overlying the more highly oxidized tantalum pentoxide layer; and coupling the first electrode of the transistor to the first conductive layer.
In another aspect, the invention provides a method of forming a capacitor. The method includes the steps of providing a substrate carrying a first conductive layer; forming a first metal oxide layer overlying the first conductive layer, the first metal oxide layer being substoichiometric; defining a second metal oxide layer by exposing the first metal oxide layer to sulfur trioxide under reaction conditions effective to oxidize the first metal oxide layer; and forming a second conductive layer overlying the second metal oxide layer.
In a further aspect, the invention provides a method of increasing the oxygen content of a substoichiometric metal oxide layer. The method includes the steps of placing the substoichiometric metal oxide layer in a processing station; and exposing the substoichiometric metal oxide layer, while the substoichiometric metal oxide layer is in the processing station, to sulfur trioxide under reaction conditions effective to oxidize the substoichiometric metal oxide layer.
In yet another aspect, the invention provides a method of forming a selected metal oxide layer overlying a substrate. The method includes the steps of forming a first metal oxide layer having a first oxygen content overlying the substrate; and conditioning the first metal oxide layer with sulfur trioxide to define the selected metal oxide layer having a second oxygen content, wherein the second oxygen content is greater than the first oxygen content.
In still another aspect, the invention provides a method of forming a computer. The method includes the steps of providing a data input device; providing a data output device; providing computing circuitry coupled to the data input and output devices, the computing circuitry including a memory cell. The memory cell is formed by a method which includes the steps of providing a transistor on a first portion of a substrate, the transistor having a first electrode; forming a first conductive layer on a second portion of the substrate; forming a dielectric layer comprising substoichiometric tantalum pentoxide having a first oxygen content, the dielectric layer overlying the first conductive layer; conditioning the dielectric layer with sulfur trioxide to define a substantially stoichiometric tantalum pentoxide layer having a second oxygen content, wherein the second oxygen content is greater than the first oxygen content; forming a second conductive layer overlying the substantially stoichiometric tantalum pentoxide layer; and coupling the first electrode of the transistor to the first conductive layer.
In another aspect, the invention provides a composition that includes a metal oxide layer in contact with sulfur trioxide.
In preferred embodiments of the above aspects, the memory cell is a dynamic random access memory. The substrate may contain silicon. The first conductive layer may be formed, at least in part, of a material selected from a conductive metal, a conductive metal compound, and a conductive metal alloy. The first conductive layer may be formed, at least in part, of a material selected from platinum, ruthenium, palladium, iridium, rhenium, rhodium, gold, silver, ruthenium, oxide, tin oxide, indium oxide, rhenium oxide, osmium oxide, rhodium oxide, iridium oxide, doped tin oxide, indium oxide, zinc oxide, YBa2Cu3O7xe2x88x92x, (La,Sr)CoO3, and SrRuO3. The dielectric layer may be formed by chemical vapor deposition or sputtering, among other possible techniques. The conditioning step may be performed at a temperature ranging from 100xc2x0 to 600xc2x0 C., at a pressure ranging from 0.1 to 10 atmospheres, for a time period of at least 10 minutes, typically 10 to 120 minutes. The stoichiometric tantalum pentoxide layer may have a thickness ranging from 5 to 200 Angstroms. The dielectric constant of the conditioned tantalum pentoxide layer typically ranges from 15-23. The second conductive layer may include a material selected from a conductive, metal, a conductive metal compound, and a conductive metal alloy, where examples of these are provided above.
These and other aspects of the invention will be further described herein in connection with the following drawings and detailed description.